The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including column redundancy decision circuitry having a block writing capability.
Conventional semiconductor memory devices include one having column redundancy decision circuitry capable of writing data in a plurality of column addresses at the same time (generally referred to as block writing). The problem with the conventional redundancy decision circuitry is that it needs the same number of fuses as the number of columns for block writing. It follows that when the number of replacements of a redundancy column or the number of columns for block writing is increased with an increase in the capacity of the memory device, the area which the redundancy decision circuitry occupies increases noticeably.
Technologies relating to the present invention are disclosed in, e.g., Japanese Patent Laid-Open Publication Nos. 63-138599, 4-65915, and 9-204793.